Course Description

Everyone who ever designed an embedded system or a communication protocol involving several components executing simultaneously has experienced that such software is inherently susceptible to bugs. Typical problems that occur are race conditions, deadlocks, and unexpected interplay between different components. Due to the parallel nature of these systems, it notoriously hard to detect such bugs using testing (timing, e.g., plays a crucial role). This course is designed to provide an introduction to the problems that arise in the design of such systems. It provides ways to model such systems and reason about them.

Where to begin and what to do first?

First time to class? Proceed to the Orientation on the course.
Returning student? Continue to the classroom and Start Here!

System Validation